AMD's Zen 7 'Grimlock' CPUs to Utilize TSMC's 1.4nm Node
AMD's next-generation Zen 7 'Grimlock' CPUs will reportedly utilize TSMC's 1.4nm node. The company is also considering new packaging technology for the chips, with some sources mentioning the use of TSMC 1.4nm process tech and FOPLP packaging, although this is reportedly under evaluation. The new CPUs are scheduled for release in 2028 but specific details about the packaging are still under consideration.
Supply chain leaks surfaced this week suggest AMD's next-generation Zen 7 core complex die, codenamed "Grimlock," is targeting TSM's 1.4nm A14 process node for a production window around 2028. According to TrendForce, Powertech Technology is also reportedly evaluating fan-out panel-level packaging (FOPLP) for the Zen 7 series, though that packaging decision is not yet final. AMD has not officially confirmed the Grimlock codename, the A14 node selection, or the 2028 launch window; all details originate from Taiwanese supply chain and industry sources.
TSMC's A14 node is the company's 1.4nm-class process, successor to N2, and is expected to enter pilot production in 2027 before ramping to volume manufacturing in 2028. The node promises meaningful transistor density gains and power-efficiency improvements over N2, which itself underpins AMD's current Zen 5 generation. FOPLP is a panel-level advanced packaging approach that replaces circular wafers with large rectangular panels, potentially reducing substrate cost and enabling denser chiplet integration at scale. Powertech Technology is one of Taiwan's leading outsourced semiconductor assembly and test (OSAT) firms, and its involvement signals that AMD is actively exploring packaging options beyond TSMC's in-house CoWoS and SoIC stacks for future high-core-count designs. Critically, FOPLP for compute chiplets at this complexity level remains unproven in mass production, and the evaluation status reported by TrendForce implies no commitment has been made.
If the A14 node targeting holds, the Zen 7 generation would position AMD at the leading edge of TSMC's logic roadmap at roughly the same time Intel aims to ramp its own 14A node through Intel Foundry. That convergence makes TSMC's advanced-node capacity, and how AMD secures wafer allocation relative to Apple, NVIDIA, and other A14 customers, a key variable to watch. On the packaging side, a successful FOPLP adoption could meaningfully reduce per-unit cost for large chiplet assemblies, a recurring margin pressure for AMD's client and data-center CPU lines. Investors and analysts should watch for any official TSMC A14 capacity announcements, AMD roadmap disclosures at future analyst days, and Powertech earnings commentary on FOPLP ramp timelines as concrete signals behind today's unconfirmed leak.
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